The present invention relates generally to a semiconductor device, and more particularly to a semiconductor device suited to a low-noise type transistor, for example, a MOSFET and an integrated circuit using the same.
A low-noise characteristic is especially required of, e.g., an amplifier circuit among a variety of circuits included in a semiconductor device.
A comb-shape structured transistor has hitherto been used as a transistor in which the above low-noise characteristic is actualized.
This comb-shape structured transistor having, as illustrated in a plan view of FIG. 9, source regions 3 and drain regions 4 which have alternately been formed with strips of gate electrodes 7 extending therebetween, is configured as a whole in a laterally elongate rectangular shape. That is, the plurality of gate electrodes 7 alternately extend across long sides of this rectangle, and contact holes 9 and electrodes 10 are so provided as to connect the adjacent gate electrodes to each other on both sides of the long sides of the source-drain regions.
In the case of the comb-shape structured transistor, for reducing a resistance of the gate electrode 7, a silicide layer is stacked on a polysilicon layer to decrease the resistance, thereby reducing noises.
Incidentally, in the amplifier circuit including the comb-shape structured transistor of which the low-noise characteristic described above is required, there exists an equivalent circuit in which a series circuit constructed of a substrate resistance from an interconnection connected to an input stage thereof to a substrate contact via an inter-layer film capacitance existing under a pad, is connected to the input stage. A structure thereof will be explained with reference to FIG. 10.
Referring to FIG. 10, a field oxide layer 2 for device isolation on the surface of a semiconductor substrate 1 so as to surround device regions 3, 4. A part of the field oxide layer 2 is formed with an opening 5 for taking out potential of the substrate, and the substrate surface at this opening 5 is provided with a high-concentration layer 6, exhibiting the same conductivity type as that of a well, for determining potential of a substrate or well.
A gate polysilicon layer 7 is provided on the device regions 3, 4 so as to extend over some of the field oxide layer 2 surrounding the device regions 3, 4, and the whole is covered with an inter-layer insulating film 8.
A contact hole 9 is formed in the inter-layer insulating film 8 at the location corresponding to the gate polysilicon layer 7, and the contact hole 9 is connected to a metal interconnection 10. Furthermore, a contact hole 11 is provided corresponding to the high-concentration layer 6 for taking out the well potential, and the layer 6 is connected via this contact hole 11 to an interconnection 12 for taking out the well potential.
Furthermore, a second inter-layer insulating film 13 is provided on those elements, a contact hole 14 is formed corresponding to the gate interconnection 10, and an interconnection 15 for connecting the gate electrode is provided on the second inter-layer insulating film 13.
Based on this construction, however, as illustrated in FIG. 10, there is configured an equivalent circuit in which a substrate resistance R1 and an inter-layer film capacitance Cl are connected in series between the well potential taking-out interconnection 12 and the gate interconnection 15.
Then, thermal noises caused by this substrate resistance R1 enter the input stage of the transistor via the inter-layer film capacitance C1, resulting in deterioration of the noise characteristic. In particular, the deterioration of the noise characteristic due to the substrate resistance becomes conspicuous in a MOSFET with a high gate input impedance.